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2024年7月19-21日，“发展芯技术，智算芯未来”第二届中国计算机学会芯片大会在上海富悦大酒店成功举办。大会由CCF主办，CCF下属四个专委会与CCF上海分部承办。近两千名专家学者、研究人员和企业代表亲临现场，共同探讨芯片设计与EDA、新型体系架构、容错计算、新兴计算机工程与工艺等方面的理论创新、技术研发、应用示范与产业发展话题。
Placement and Routing For A Field Programmable Multi-Chip Module
Placement Routing Field Programmable Multi-Chip Module
2015/8/14
Placement and Routing For A Field Programmable Multi-Chip Module.
On-Chip True Random Number Generation in Nanometer CMOS
True Random Number Generation Process Variation Circuit calibration
2014/12/8
On-chip True Random Number Generator (TRNG) forms an integral part of a number of cryptographic systems in multi-core processors, communication networks and RFID. TRNG provides random keys, device id ...
ASU scientists improve chip memory by stacking cells
ASU scientists chip memory stacking cells
2009/12/23
Scientists at Arizona State University have developed an elegant method for significantly improving the memory capacity of electronic chips.Led by Michael Kozicki, an ASU electrical engineering profes...
Hybrid automatic repeat request (HARQ) is used in high-speed uplink packet access (HSUPA) to increase the data rate. Chase combining is the simplest of HARQ algorithms. It provides a time diversity an...
Simulation of Crosstalk in High-Speed Multi-Chip Modules
Crosstalk High-Speed Multi-Chip Modules
2010/12/14
Simulation results of the electrical performance at 1 GBits/sec of a number of different off-chip interconnection architectures are presented with emphasis given to the dependence of crosstalk and sig...
Humidity Effect on Chip Capacitors With Al2O3 Multistage Anodised Films
Chip capacitors aluminum oxide capacitors humidity effects
2010/12/16
In this paper the properties of capacitors with porous-barrier and barrier-type Al2O3 layers under humidity tests are described and compared. The capacitance, conductance and dissipation factor of the...
Electrical Modelling of Multilevel On-Chip Interconnections for High-Speed Integrated Circuits
Multilevel On-Chip Interconnections High-Speed Integrated Circuits
2010/12/16
A method for the electrical parameters analysis and modelling of lossy-coupled multilayer on-chip interconnection lines at high bit rates is presented in detail. It can be used by the VLSI designer to...
Description and Performance of a Novel Concept “Single Level” Ceramic Chip Carrier
a Novel Concept Single Level Ceramic Chip Carrier
2010/12/27
Two different designs of ceramic chip carriers are discussed. A carrier capable of being hermetically sealed has been developed which uses a glass seal combined with an epoxy bonded chip. A second car...
Direct Chip Mounting — A Challenge to the Design Engineer
Direct Chip Mounting the Design Engineer
2010/12/27
In this paper alternatives to printed circuit board technology with insulated wiring (multilayers), and the mounting of chips from film carriers, are evaluated. These principles have a good possibilit...
Surface Mounting of Leadless Chip Carriers on Various Printed Circuit Board Type Substrates
Chip Carriers Printed Circuit Board Type Substrates
2010/12/27
The effect of extended thermal cycling on the reliability of joints between ceramic leadless chip carriers and various printed circuit board type substrates is examined. Test results indicate success ...
Reliability Considerations of Flip Chip Components for Automotive Electronic Applications
Flip Chip Components Automotive Electronic Applications
2010/12/28
Electronic devices for automotive electronic applications have to be operated under extreme environmental conditions and therefore are required to have higher reliability compared with general electro...
Properties of Coplanar Type MIS-SIM Structure Chip Capacitor
Coplanar type MIS-SIM structure low resistivity silicon
2011/1/10
Coplanar type MIS-SIM structure has been designed and fabricated on low resistivity silicon.
The two electrodes are deposited on the thermal oxide grown on silicon. This structure could be analysed b...
It is shown that in order to interconnect more than 25 I.C. chips (SSI and MSI) or to use LSI chips together with other kind of chips, the chips must be tested before mounting. Then only TAB- or CC-te...