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Hybrid Prefix Adder Architecture for Minimizing the Power Delay Product
Parallel Prefix Adder (PPA) Dot operator Semi-Dot operator
2010/2/2
Parallel Prefix addition is a technique for improving
the speed of binary addition. Due to continuing integrating intensity
and the growing needs of portable devices, low-power and highperformance
...
Critical Path Delay and Net Delay Reduced Tree Structure for Combinational Logic Circuits
Synthesis Delay optimization Binary logic tree Logic depth
2010/2/2
In this paper, a technique for synthesizing binary tree
structure of a non-regenerative logic circuit functionality is proposed,
that achieves delay optimization by reducing the logic depth. It also...